In deep submicron technology, System-on-Chip (SoC) products may require a high-speed and low-power embedded memory to support increased storage capability. Typically, static random access memory (SRAM) has been widely used; more precisely a single-port SRAM, which allows one read or one write at a single clock cycle has generally been used. The field of SRAM devices has led to the development of a multi-port SRAM capable of performing multiple read and write operations in a single clock cycle.
A multi-port SRAM may greatly contribute to parallel operation and it is typically used as a buffer memory in multimedia applications or a data cache in a multi-core processor. The demand for multi-port SRAMs and other multi-port memory devices is increasing to accommodate high-speed communications and image processing. The capability to access the memory simultaneously can help to ease system speed bottlenecks and may directly improve system performance.
In general, one unit memory cell of a single-port SRAM device may be composed of six transistors, that is, two load transistors, two drive transistors, and two active transistors, to perform the read and write operations sequentially. In contrast, a multi-port SRAM device may be configured with additional active, transistors, beyond those of the general single-port SRAM, so as to support multiple simultaneous read and write operations. Such multiple access usage may lead to various difficulties. In a multiple access operation, for example, when a first port is used for a write operation and a second port is used for a read operation at the same time, they may interfere with each other to cause a characteristic drop in the SRAM cell. This may be observed, for example, during address contention, either full address contention or row address contention. Such interference may cause data errors, for example, an unsuccessful write operation.